1. Field of the Invention
The present invention relates to a digital-to-analog converter. More particularly, the present invention relates to a switched capacitor digital-to-analog converter.
2. Description of Related Art
Generally, for an audio-visual system, resolution of a digital-to-analog converter (DAC) therein used for data conversion is a key factor that influences music quality presented by the audio-visual system.
Therefore, a switched capacitor digital-to-analog converter (SC-DAC) with a high resolution is developed based on a conventional technique to cope with demand of market. The SC-DAC may convert a series of single/multi-bit digital signals represented by delta-sigma into analog signals. A circuit structure and an operation principle of the conventional SC-DAC will now be described more fully with reference of an accompanying drawing.
FIG. 1 is a circuit diagram illustrating a conventional single ended structure SC-DAC 100. Referring to FIG. 1, the SC-DAC 100 includes an operation amplifier 110, capacitors 120 and 130, and switches 140 and 150. A non-inverting input terminal 111 of the operational amplifier 110 is used for receiving a reference level Vmid1, one terminal of the capacitor 120 is coupled to an inverting input terminal 112 of the operational amplifier 110, and another terminal of the capacitor 120 is coupled to an output terminal 113 of the operational amplifier 110.
A first terminal 141 of the switch 140 is used for receiving a reference level Vmid2, and a second terminal 142 of the switch 140 is coupled to the inverting input terminal 112 of the operational amplifier 110. One terminal of the capacitor 130 is coupled to a third terminal 143 of the switch 140, and another terminal of the capacitor 130 is coupled to a first terminal 151 of the switch 150. A second terminal 152 of the switch 150 is used for receiving a signal VP (generally having a logical high level VDD, and is supplied from an external voltage source which is not shown in FIG. 1), a third terminal 153 of the switch 150 is used for receiving a signal VN (generally having a logical low level 0V, and is supplied from the external voltage source), and a fourth terminal 154 of the switch 150 is coupled to the output terminal 113 of the operational amplifier 110.
In the conventional technique, to maximize an amplitude of an analog signal Vo converted by the SC-DAC 100, i.e. 0˜VDD, the reference levels Vmid1 and Vmid2 are generally designed to be equal, and to be a half of the logical high level VDD (i.e. ½×VDD). Moreover, switching operations of the switches 140 and 150 are mainly controlled by a control unit 160.
In the circuit structure of FIG. 1, when the control unit 160 detects a state of a digital signal (having a signal digital logic bit, for example) is a series of logical high/low levels VDD/0V, the control unit 160 then controls the first terminal 141 of the switch 140 to electrically connect to the third terminal 143 thereof, and controls the first terminal 151 of the switch 150 to electrically connect to the second terminal 152/the third terminal 153 thereof during a first period (which may also be referred to as a charge period). Therefore, the capacitor 130 is then stored with charges corresponding to a level difference between the reference level Vmid2 (i.e. ½×VDD) and the signal VP (i.e. VDD)/VN (i.e. 0V) during the first period.
Next, during a second period (which may also be referred to as a dump period), the control unit 160 controls the second terminal 142 of the switch 140 to electrically connect to the third terminal 143 thereof, and controls the first terminal 151 of the switch 150 to electrically connect to the fourth terminal 154 thereof. Thus, charges stored in the capacitor 130 during the first period are now transferred to the capacitor 120. Therefore, theoretically, the analog signals Vo corresponding to the series of logical high/low levels VDD/0V digital signals are then truly reflected on the output terminal 113 of the operational amplifier 110. Wherein, the first period and the second period form a clock cycle of the SC-DAC 100.
However, since the level difference formed by the charges stored in the capacitor 130 during each second period is Vo(t)−Vmid1, and Vo(t) is a signal varied with time (t), during a very next first period, the capacitor 130 then release a signal dependent current to the external voltage source providing the signal VP/VN, namely, the external voltage source providing the signal VP/VN takes the capacitor 130 as a signal dependent loading. Accordingly, a signal dependent voltage ripple may be appeared on the reference voltage VP/VN, and an output signal of the SC-DAC 100 is direct proportional to the reference voltage VP/VN, so that the voltage ripple may be exerted to an output of an ideal digital-to-analog converter, and therefore the analog signal Vo output from the output terminal 113 of the operational amplifier 110 may have a so-called harmonic distortion phenomenon.
To effectively solve the harmonic distortion of the analog signal Vo, a digital-to-analog converter (DAC) circuit is disclosed in a U.S. Pat. No. 6,573,850 by Pennock. According to the DAC circuit disclosed by Pennock, before the capacitor 130 stores the charges, the residual charges of the capacitor 130 generated during a former clock cycle may all be discharged or may be maintained to fixed charges, so that when the capacitor 130 stores the charges, the external voltage source providing the signal VP/VN then may no be influenced by the signal dependent loading caused by the capacitor 130, and therefore the harmonic distortion of the analog signal converted by the conventional SC-DAC then may be effectively solved.
However, since according to the DAC circuit disclosed by Pennock, before the capacitor 130 stores the charges, the residual charges of the capacitor 130 generated during the former clock cycle thereof have to be totally discharged or to be maintained to the fixed charges, a clock cycle of the DAC circuit disclosed by Pennock is relatively greater than that of the SC-DAC 100 of FIG. 1, and therefore it has a shortage of low conversion speed.
Besides, a DAC circuit disclosed by Frith et al. in a U.S. Pat. No. 6,952,176 is provided to solve the harmonic distortion of the analog signal converted by the conventional SC-DAC. Such circuit structure is designed to be a differential structure, and only after each 2 clock cycles, may the harmonic distortion of the analog signal converted by the conventional SC-DAC be approximately solved (not totally solved, actually). Therefore, the DAC circuit disclosed by Frith et al. not only has a complicated circuit structure, but also cannot eliminate the influence of the signal dependent loading for each clock cycle.